1) Field of the Invention
The present invention relates to a differential M phase shift keying optical receiving circuit, more particularly, to a differential M phase shift keying optical receiving circuit suitable to be applied to an optical receiver in an optical communication system.
2) Description of the Related Art
Recently, as the Internet becomes more widely used, demands for wider band of an optical communication network have been increasing. Since the optical communication network is used in core network trains or the like, it should be adapted to a long distance communication and a high-speed communication with a wide band. However, according to conventional methods, it is assumed that there is limitation of possibility of wider bands due to influences of chromatic dispersions of optical fibers and nonlinear effects.
In order to solve this problem, an effort to widen the band by devising optical signal modulation methods not by directly suppressing its physical effects is proposed (for example, see US Patent Application Laid-Open No. 2004/0081470). According to this proposal, the method used as an optical signal modulation method is a differential M phase shift keying upon M=2n where n is an integer equal to or more than 2. Further, a method in which the n is set as n=2 (M=4) is called DQPSK (Differential Quadrature Phase Shift Keying) modulation system.
FIG. 15 is a diagram showing a typical structure of a DQPSK optical receiving circuit 100 of DQPSK modulation system. According to the optical receiving circuit 100 shown in FIG. 15, an optical splitter 101 bifurcates an optical signal modulated by the DQPSK modulation system and a π/4 delay interferometer 102-1 and a −π/4 delay interferometer 102-2 respectively perform a delay interfering process for the optical signal bifurcated by the optical splitter 101. Further, balanced photodiodes 103-1, 103-2 convert the light which is delay interfered in the delay interferometers 102-1, 102-2 into electronic signals (current signals).
A DQPSK signal employs optical phases of π/4, 3π/4, −π/4, and −3π/4 as a relative phase value for a signal of one prior symbol. The π/4 delay interferometer 102-1 and the −π/4 delay interferometer 102-2 relatively give a π/2 differential delay to the optical signal from the optical splitter 101. Accordingly, the balanced photodiode 103-1 of line #1 in which the π/4 delay interferometer 102-1 is provided outputs an electronic signal in which phase changes of π/4 and −3π/4 of the optical signal are converted into intensity change. On the other hand, the balanced photodiode 103-2 of line #2 in which the −π/4 delay interferometer 102-2 is provided outputs an electronic signal in which phase change of −π/4 and 3π/4 of the optical signal (orthogonal component for phase changes of π/4 and −3π/4) are converted into intensity change.
Transimpedance amplifiers (TIAs) 104-1, 104-2 respectively convert the current signals from the balanced photodiodes 103-1, 103-2 into voltage signals. Then, a clock and data recovery (CaDR) unit 105 digitizes the electronic signals from the TIAs 104-1, 104-2 and a multiplex unit (MUX) 106 performs a logical process or the like to restore the original signal.
Here, the CaDR unit 105 includes a clock recovery (CR) 105a for extracting a clock signal from an input signal of line #1 from the TIA 104-l and DFFs (D-FlipFlop) 105b, 105c for outputting, as synchronizing with the clock signal in the clock recovery 105a, digital signals in which levels of the input signals of lines #1, #2 from the TIAs 104-1, 104-2 are identified.
As described above, according to the DQPSK optical receiving circuit 100 shown in FIG. 15, input signals of two lines (line #1, line #2) are input in the CaDR unit 105 and the CaDR unit 105 is configured to extract a common clock from the input signal of line #1 and identifies input signals of lines #1 and #2.
However, according to the DQPSK optical receiving circuit 100 shown in FIG. 15, a clock signal to be extracted is deteriorated when gain property of the optical front-end unit (reference numerals 102-1, 103-1) in line #1 or an error of delay property occurs in delay interferometer 102-1. Accordingly, there is a problem that, even when the gain property and the delay property in the optical front-end unit (reference numerals 102-2, 103-2) in line #2 are normal, identification property of not only the signal of line #1 but also the signal of line #2 may be deteriorated in the digitization unit 105.
Further, when a gain property reduction or an error delay property occurs, as described above, in the optical front-end unit of lines #1, #2, as shown in FIG. 16, a phase shifting t1 (that is, a phase shifting π/2 from phase difference) of the input signals of lines #1, #2 addressed to the digitization unit 105 may occur. This phase shifting corresponds to a relative identifying shift t2 in the digitization unit 105. That is, there is another problem that, regarding the signal of line #1 in which clock C is extracted from a signal of the own line, identification can be implemented at an appropriate identification timing in the DFF 105b; however, regarding the signal of line #2 in which the clock is not extracted from the signal of the own line, an effective identification phase margin in the DFF 105c may be deteriorated.